Semiconductor memory device

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S189070

Reexamination Certificate

active

07859939

ABSTRACT:
A semiconductor memory device includes a clock input unit configured to receive a first clock and a second clock from the external. The memory device further includes a frequency conversion unit configured to convert a frequency of the second clock so that the frequency of the second clock becomes identical to a frequency of the first clock, a phase comparison unit configured to compare a phase of the first clock with that of a clock outputted from the frequency conversion unit, and output a comparison signal corresponding to the comparison result, a logic level change unit configured to change a logic level of a training information signal when a logic level of the comparison signal is fixed for a given time after being changed, and a signal transfer unit configured to transfer the training information signal to the external.

REFERENCES:
patent: 6000022 (1999-12-01), Manning
patent: 6768698 (2004-07-01), Kono
patent: 1020030080534 (2003-10-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Jan. 26, 2010.

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