Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-05-05

2009-12-01

Phung, Anh (Department: 2824)

Static information storage and retrieval

Powering

C365S189090, C365S210120, C365S185130, C365S185040, C365S024000

Reexamination Certificate

active

07626883

ABSTRACT:
During a stand-by state in which power supply is cut off, a high-voltage power supply control circuit isolates a global negative voltage line transmitting a negative voltage and a local negative voltage line provided corresponding to each respective sub array block from each other and isolates a global ground line and a local ground line transmitting a ground voltage from each other. These local ground line and local negative voltage line are charged to a high voltage level through a high voltage line before cut-off from the corresponding power supply. A leakage current path from a word line to the negative voltage line or the ground line is cut off, so that the word line in a non-selected state can reliably be maintained at a non-selection voltage. Thus, in a low power consumption stand-by mode, data stored in a memory cell can be held in a stable manner.

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patent: 2000-173263 (2000-06-01), None
patent: 2005-353244 (2005-12-01), None
Watanabe, Naoya et al., “An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester,” IEICE Trans. Electron., vol. E86-C, No. 4 Apr. 2003.

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