Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-05-17

2009-02-24

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189090

Reexamination Certificate

active

07495965

ABSTRACT:
A voltage switching circuit used in a row decoder includes: PMOS transistor P2and high-voltage NMOS transistor D3connected in series between VRDEC and TG; PMOS transistor P1and high-voltage NMOS transistor D2connected in series between VRDEC and NA; NMOS transistor N2and high-voltage NMOS transistor D6connected in series between TG and Vss to be driven by decode output Ab; and NMOS transistor N1and high-voltage NMOS transistor D5connected in series between NA and Vss to be driven by decode output Aa. Gates and drains of P1and P2are cross-coupled. Gates of D3and D2are coupled to TG and NA, respectively.

REFERENCES:
patent: 5652726 (1997-07-01), Tsukude et al.
patent: 6181606 (2001-01-01), Choi et al.
patent: 6608788 (2003-08-01), Ma et al.
patent: 6700429 (2004-03-01), Kanno et al.
patent: 6847555 (2005-01-01), Toda
patent: 6885583 (2005-04-01), Tanaka
patent: 7085162 (2006-08-01), Nakamura et al.
patent: 2005/0232013 (2005-10-01), Kawai et al.
patent: 2006/0239073 (2006-10-01), Toda
patent: 8-167290 (1996-06-01), None
patent: 2003-152096 (2003-05-01), None
patent: 2005-285161 (2005-10-01), None

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