Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-03-15

2009-12-29

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S094000, C365S230030, C365S103000, C365S104000

Reexamination Certificate

active

07639559

ABSTRACT:
In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current. Consequently, the time required for charging or discharging the dummy bit line differs from the desired time, and therefore, it has been unable to set optimum operation timing. To solve these problems, a semiconductor memory device of the present invention includes a dummy memory cell array in which source lines of dummy memory cells are charged simultaneously by a charge circuit configured similarly to a dummy bit line charge circuit, thus suppressing off leak current and performing appropriate timing generation.

REFERENCES:
patent: 5757709 (1998-05-01), Suminaga et al.
patent: 5886937 (1999-03-01), Jang
patent: 2004/0151033 (2004-08-01), Takazawa et al.
patent: 2006/0120201 (2006-06-01), Kurata et al.
patent: 836895 (1996-02-01), None

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