Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185050

Reexamination Certificate

active

07630243

ABSTRACT:
A virtual ground type semiconductor memory device comprises: a memory cell array in which nonvolatile memory cells each including a first electrode, a pair of second electrodes, and a charge retention part are arranged in row and column directions like a matrix; a read circuit for selecting a pair of the first and second bit lines connected to a selected memory cell to be read, applying first and second read voltages to the selected first and second bit lines, respectively, and detecting a magnitude of a memory cell current flowing in the selected memory cell, at the time of reading; a voltage applying means for applying the second read voltage to a second adjacent bit line adjacent to the selected second bit line on the opposite side of the first bit line; and a short-circuit means for short-circuiting the selected second bit line and the second adjacent bit line.

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International Search Report mailed Dec. 19, 2006, directed to counterpart international application No. PCT/JP2006/321819; 2 pages.
Roy et al. (1997). “A New Flash Architecture With a 5.8λ2Scalable AMG Flash Cell,”Symposium on VLSI Technology Digest of Technical Papers:67-68.

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