Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-11-28

2009-06-02

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185220, C365S185180, C365S185050, C365S230060, C365S242000

Reexamination Certificate

active

07542349

ABSTRACT:
The invention provides a semiconductor memory device where a circuit area is minimized and a voltage drop in a high voltage supply path to a source line is reduced. An output of a high voltage generation circuit is connected to a source line through a first transfer gate, and connected to a word line through a second transfer gate. The first transfer gate is configured of a P-channel type MOS transistor of which on and off are controlled by a write enable signal, and the second transfer gate is configured of a P-channel type MOS transistor of which on and off are controlled by an erase enable signal. A third transfer gate supplying the output of the high voltage generation circuit to the source line without through a high voltage switching circuit is further provided. The third transfer gate is configured of a P-channel type MOS transistor and an inverted output of the high voltage switching circuit is applied to the gate thereof.

REFERENCES:
patent: 6954400 (2005-10-01), Lakhani et al.
patent: 7133323 (2006-11-01), Lakhani et al.
patent: 2000-173278 (2000-06-01), None

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