Semiconductor memory device

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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Details

C324S763010

Reexamination Certificate

active

07489153

ABSTRACT:
The invention relates to a semiconductor memory device, which can be operated in a normal operating mode and a test mode, comprising: data terminals and data clock terminals; input receivers for processing the signal arriving via the respective terminal, a respective input receiver being assigned to a data terminal and/or data clock terminal; at least one test circuit, a respective test circuit being assigned to an input receiver and the test circuit being designed for determining at least one predetermined property of the assigned input receiver.

REFERENCES:
patent: 3982190 (1976-09-01), Schaefer
patent: 5095267 (1992-03-01), Merrill et al.
patent: 6166607 (2000-12-01), Schoellkopf
patent: 6426641 (2002-07-01), Koch et al.
patent: 2002/0125903 (2002-09-01), Lovett
patent: 2003/0030461 (2003-02-01), Oberle et al.
patent: 2007/0001697 (2007-01-01), Dobberpuhl et al.
patent: 0 953 987 (1999-11-01), None
German Patent Office Examination Report dated Feb. 10, 2005.

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