Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185280

Reexamination Certificate

active

07471563

ABSTRACT:
Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.

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SuperFlash EEPROM Technology, Technical Paper dated Nov. 2001, pp. 1-8 from 2002 Silicon Storage Technology Inc.
Sasago et al., “90-nm-mode multi-level AG-AND type flash memory with cell size of true 2 F2/bit and programming throughput of 10 MB/s”, IEEE International Electron Devices Meeting, 2003, pp. 29-32.
Arai et al., “High-Density (4.4 F2) NAND Flash Technology UsingSuper-ShallowChannelProfile (SSCP) Engineering”, International Electron Devices Meeting, 2000, p. 775-778.
Kobayashi et al., “A Giga-Scale Assist-Gate (AG)-AND-Type Flash Memory Cell with 20-MB/s Programming Throughput for Content-Downloading Applications”, International Electron Devices Meeting, 2001, pp. 29-32.
Eitan et al., “Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?”, International Conference on Solid State Devices and Materials, 1999, pp. 522-524.

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