Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-07-03

2008-12-09

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Multiple values

C365S185090, C365S185230, C365S200000

Reexamination Certificate

active

07463515

ABSTRACT:
A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a row decoder configured to select a memory cell in the memory cell array, the row decoder including a flag latch, in which a bad block flag is set for a bad block in the memory cell array; a sense amplifier configured to sense data of a selected memory cell in the memory cell array; and an output circuit configured to output read data in the sense amplifier, the output circuit including an output data fixing circuit configured to fix an output data at a logic level in accordance with the bad block flag.

REFERENCES:
patent: 6404683 (2002-06-01), Yumoto
patent: 6426892 (2002-07-01), Shibata et al.
patent: 7313022 (2007-12-01), Takeuchi et al.
patent: 2008/0123409 (2008-05-01), Shirakawa
patent: 2003-109396 (2003-04-01), None
U.S. Appl. No. 11/773,280, filed Jul. 3, 2007, Shirakawa et al.
U.S. Appl. No. 12/040,155, filed Feb. 29, 2008, Tokiwa.

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