Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-06-11

2008-12-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S230080

Reexamination Certificate

active

07466619

ABSTRACT:
A semiconductor memory device includes a plurality of banks #0to #3, a predecoder that generates a predecode signal, first latch circuits, each of which is assigned to the banks, that hold a first portion of the predecode signal, a main decoder that is assigned in common to the two banks, and receives a second portion of the predecode signal and outputs of the first latch circuits. The main decoder includes latch circuits that hold by each bank a decoded signal obtained by decoding the second portion of the predecode signal. In the present invention, an address through predecoder is used to latch a predecode signal, and hence it becomes possible to share one portion of the predecode signal between the banks.

REFERENCES:
patent: 6944081 (2005-09-01), Takahashi et al.
patent: 2001/0038569 (2001-11-01), Fujisawa et al.
patent: 08-255479 (1996-10-01), None
patent: 11-163-48 (1999-01-01), None
patent: 11-203858 (1999-07-01), None
patent: 2000-113670 (2000-04-01), None
patent: 2000-251471 (2000-09-01), None

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