Semiconductor memory device

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185240, C365S185190, C365S185290

Reexamination Certificate

active

07349249

ABSTRACT:
A semiconductor memory device includes a memory cell array with memory cells arranged therein, each memory cell storing data defined by threshold voltage thereof, wherein the memory cell array includes first and second areas; the first area stores multi-value data written with plural write steps; and the second area stores binary data defined by first and second logic states, threshold levels of which are controlled through the plural write steps adapted to the multi-value data write.

REFERENCES:
patent: 5191556 (1993-03-01), Radjy
patent: 6288935 (2001-09-01), Shibata et al.
patent: 6426892 (2002-07-01), Shibata et al.
patent: 6496412 (2002-12-01), Shibata et al.
patent: 2001-93288 (2001-04-01), None

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