Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-06-29

2008-03-18

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185170, C365S185230, C365S185240, C365S211000

Reexamination Certificate

active

07345913

ABSTRACT:
A semiconductor memory device, comprising: a memory cell array of a plurality of memory cell units, each memory cell unit including a plurality of serially connected memory cells formed on the same well region, each memory cell having a floating gate and a control gate stacked, said serially connected memory cells having one end serially connected to a first selection gate transistor, said serially connected memory cells having the other end connected to a common source line via a second selection gate transistor; a sense amp connected to one end of said first selection gate transistor via a bit line and operative to read data out of said memory cell array; and wherein a voltage applied to said well region and said source line varies to cancel a change of threshold of said memory cells depending on the temperature.

REFERENCES:
patent: 6667904 (2003-12-01), Takeuchi et al.
patent: 6970391 (2005-11-01), Watanabe et al.
patent: 2007/0008779 (2007-01-01), Isobe
patent: 2002-170391 (2002-06-01), None
U.S. Appl. No. 11/836,378, filed Aug. 9, 2007, Isobe.

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