Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185180

Reexamination Certificate

active

11126330

ABSTRACT:
Based on a continuous erase start signal outputted, in response to an inputted continuous erase command, from a continuous erase control circuit, a shift circuit outputs a control signal for giving instructions to execute respective data erase operation to a plurality of non-volatile memory circuits sequentially, and when the data erase operation in all of the non-volatile memory circuits has been completed, the shift circuit outputs a continuous erase completion signal. Thereby, the data erase operation in all of the non-volatile memory circuits built in one chip can be continuously executed by one continuous erase command as is also the case where a single non-volatile memory circuit is built in.

REFERENCES:
patent: 5566113 (1996-10-01), Saito et al.
patent: 5844837 (1998-12-01), Yoshikawa
patent: 6108232 (2000-08-01), Hennebois et al.
patent: 6137720 (2000-10-01), Lancaster
patent: 6906961 (2005-06-01), Eggleston et al.
patent: 2003/0145151 (2003-07-01), Matsushita
patent: 05012889 (1993-01-01), None

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