Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-07-24

2007-07-24

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189011, C365S189050

Reexamination Certificate

active

11344206

ABSTRACT:
A semiconductor memory device includes an interface unit connected to an external circuit, a data memory unit including a write data line, a read-out data line, a data control unit, and a memory block connected to the data control unit, and a read-out latch block connected between a read-out data line and the interface unit. The data control unit outputs data read out of the memory block to the read-out data line with a trailing edge of a clock being used as a trigger. The read-out latch block latches the data with a trailing edge of another clock, which is generated at least one cycle after the trailing edge of the aforementioned clock, being used as a trigger. The interface unit outputs the data to the external circuit with a leading edge of still another clock, which follows the aforementioned another clock, being used as a trigger.

REFERENCES:
patent: 6160275 (2000-12-01), Nishio et al.
patent: 7164601 (2007-01-01), Mitani et al.
U.S. Appl. No. 11/344,206, filed Feb. 1, 2006, Iizuka.
U.S. Appl. No. 11/344,016, filed Feb. 1, 2006, Kaku.

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