Semiconductor memory device

Static information storage and retrieval – Addressing – Plural blocks or banks

Reexamination Certificate

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C365S063000, C365S189011

Reexamination Certificate

active

11344016

ABSTRACT:
In a semiconductor memory device, sub-macros are connected sequentially onto an interface unit in which each sub-macro includes a data control unit connected to the interface unit through a global data line, a first memory block and a second memory block. The first memory block is connected to one side of the data control unit through a first local data line, and the second memory block is connected to the other side of the data control unit through a second local data line.

REFERENCES:
patent: 6157560 (2000-12-01), Zheng
patent: 6345010 (2002-02-01), Shimazaki et al.
patent: 6385121 (2002-05-01), Lee
patent: 6452824 (2002-09-01), Okamura
patent: 6603701 (2003-08-01), Mizugaki et al.
patent: 6678191 (2004-01-01), Lee et al.
patent: 2006/0200728 (2006-09-01), Nagai et al.
patent: 2002-304881 (2002-10-01), None
U.S. Appl. No. 11/344,206, filed Feb. 1, 2006, Iizuka.
U.S. Appl. No. 11/344,016, filed Feb. 1, 2006, Kaku.

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