Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S194000, C365S230060

Reexamination Certificate

active

07145803

ABSTRACT:
A semiconductor memory device includes word lines, drain lines, source lines, a memory array including plural memory cells formed from a field effect transistor, a data write circuit, a write control circuit, and a word line drive circuit, wherein the write control circuit outputs the drain drive voltage of H-level to the selected memory cell when a data write operation is commanded, and outputs the drain drive voltage of L-level when a data write operation is not commanded, and the data write circuit generates a write voltage corresponding to a logical value of data to be written into the selected memory cell based on the drain drive voltage outputted from the write control circuit, and supplies the write voltage as the source drive voltage via the source line to the selected memory cell when a data write operation is commanded by the first control signal.

REFERENCES:
patent: 6157983 (2000-12-01), Lee et al.
patent: 6243297 (2001-06-01), Nagatomo
patent: 6418067 (2002-07-01), Watanabe et al.
patent: 2000-331486 (2000-11-01), None

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