Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1996-08-29

1999-08-24

Fears, Terrell W.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523001, G11C 1300

Patent

active

059432845

ABSTRACT:
A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

REFERENCES:
patent: 5499216 (1996-03-01), Yamamoto
A 1-V 100-MHz 10-mW Cache Using a Separated Bit-Line Memory Hierarchy Architecture and Domino Tag Comparators, H. Mizuno et al, pp. 1-4.
IEEE 1990 Symposium on VLSI Circuits, A IV Operating 256--Kbit Full CMOS SRAM, A. Sekiyama et al, pp. 53-54.
1994 IEEE Symposium on Low Power Electronics, "Low-Power Design of Memory Intensive Functions", D. Lidsky et al, pp. 16-17.

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