Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185050, C365S185110, C365S185270

Reexamination Certificate

active

07061807

ABSTRACT:
A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

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