Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-12-19

2006-12-19

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S201000, C365S230060, C365S233100

Reexamination Certificate

active

07151713

ABSTRACT:
A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input.

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