Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-05-30

2006-05-30

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S222000, C365S191000

Reexamination Certificate

active

07054223

ABSTRACT:
A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.

REFERENCES:
patent: 6208577 (2001-03-01), Mullarkey
patent: 6636449 (2003-10-01), Matsuzaki
patent: 2003/0039163 (2003-02-01), Leung
patent: 2003/0072206 (2003-04-01), Chen
patent: 2004/0057315 (2004-03-01), Jain
Zensuke Matsuda. “System Memory Development Policy”, NEC Device Technology International 2002, Searched on Jun. 28, 2003, No. 65, Internet <URL> “http://www.necel.com/japanese/banner/tech/77/DTJ77NSZ.pdf”.

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