Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1988-06-07

1990-11-20

Moffitt, James W.

Static information storage and retrieval

Floating gate

Particular biasing

365182, 357 235, G11C 1134

Patent

active

049723715

ABSTRACT:
An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

REFERENCES:
patent: 4531203 (1985-07-01), Masuoka et al.
patent: 4665418 (1987-05-01), Mizutani
patent: 4835740 (1989-05-01), Sato
IEDM Technical Digest 1985, pp. 616-619, "A Single Transistor EEPROM Cell and Its Implementation in a 512K CMOS EEPROM", by Mukherjee et al.

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