Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2006-09-12

2006-09-12

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030

Reexamination Certificate

active

07106649

ABSTRACT:
A semiconductor memory device includes a memory cell array comprising a plurality of memory sub-array blocks arranged in a row direction, a plurality of sub-word lines which extend in the row direction to connect with the plurality of memory cells, a plurality of sub-word-line drivers, a plurality of sub-word-line level shifters, a first pre-decoded line group which is connected with the respective sub-word-line drivers, a second pre-decoded line group which extends across the memory sub-array block in the row direction and is connected with the sub-word-line level shifters, and a pre-row-decoder which supplies information of a selected cell to the first and second pre-decoded lines.

REFERENCES:
patent: 6067257 (2000-05-01), Kitsukawa et al.
patent: 6195305 (2001-02-01), Fujisawa et al.
patent: 6229755 (2001-05-01), Oh
patent: 6274895 (2001-08-01), Fujii et al.
patent: 6584031 (2003-06-01), Fujisawa et al.
Tohru Kimura, et al., “64Mb 6.8ns Random ROW Access DRAM Macro for ASICs”, IEEE International Solid-State Circuits Conference, 1999, Session 24, Paper WP 24.4 p. 416-417.

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