Semiconductor memory device

Static information storage and retrieval – Addressing – Sync/clocking

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Details

36523008, G11C 800

Patent

active

057485585

ABSTRACT:
A semiconductor memory device of the present invention is so constituted that, in addition to a first address register for fetching and holding an address signal in synchronous with a clock signal irrespective of read operation and write operation, a second address register is provided to hold a write address, and an address selection circuit selects the held write address to write data held in an input data register into a cell. Thereby, a late write system can be achieved in an synchronous SRAM.

REFERENCES:
patent: 5341341 (1994-08-01), Fukuzo
patent: 5550783 (1996-08-01), Stephens

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