Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-08-23

2005-08-23

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S230080

Reexamination Certificate

active

06934216

ABSTRACT:
A mode set entry circuit outputs a latch timing signal at the timing at which the combination of a plurality of commands is detected. A first address latch circuit retains mode designation data for designating the operation mode in response to the latch timing signal and outputs the retained mode designation data. Next, a second address latch circuit retains the mode designation data outputted by the first address latch circuit in response to a latch timing signal indicating the end of the commands in the combination of the plural commands, and outputs the retained mode designation data.

REFERENCES:
patent: 6522598 (2003-02-01), Ooishi
patent: 6842398 (2005-01-01), Johnson et al.
Patent Abstract of Japan 11045571 A Feb. 16, 1999.
Patent Abstract of Japan 09129824 A May 16, 1997.

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