Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-06-14

2005-06-14

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185040, C365S230030

Reexamination Certificate

active

06906960

ABSTRACT:
A semiconductor memory device includes: a plurality of banks with electrically rewritable memory cells arranged therein, the banks being configured to be simultaneously accessible in such a manner that a data write operation into a bank and a data read operation for another bank are simultaneously performed; a write-use data bus commonly disposed for the plurality of banks; a read-use data bus commonly disposed for the plurality of banks; a write circuit connected to the write-use data bus; a read circuit connected to the read-use data bus; a bank address decoder circuit for decoding external bank address signals for bank selecting to output internal bank address signals, the bank address decoder circuit having such an address conversion function that one of plural kinds of address conversions between the external bank address signals and the internal bank address signals is selectable; and a rewrite control circuit for sequence controlling a data write operation for a bank selected by the bank address decoder circuit.

REFERENCES:
patent: 5959887 (1999-09-01), Takashina et al.
patent: 6377502 (2002-04-01), Honda et al.
patent: 6418061 (2002-07-01), Kitazaki
patent: 6512693 (2003-01-01), Honda et al.
patent: 2001-60397 (2001-03-01), None
patent: 2001-325795 (2001-11-01), None

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