Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-02-15

2005-02-15

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S042000, C365S230060

Reexamination Certificate

active

06856574

ABSTRACT:
A semiconductor memory device comprises a memory-cell array for storing data, a peripheral circuit for carrying out an operation to read out or write data from or into the memory-cell array, read clock generation circuits (111, 113and115) each used for generating a read clock signal to be supplied to the peripheral circuit in the operation to read out data from the memory-cell array, write clock generation circuits (112, 114and116) each used for generating a write clock signal to be supplied to the peripheral circuit in the operation to write data into the memory-cell array. Since the pulse widths of the clock signals in read and writes are adjusted individually, margin insufficiencies of the pulse widths can be evaluated and results of the evaluation can be fed back to a design phase for, among other purposes, correction of a layout.

REFERENCES:
patent: 4890262 (1989-12-01), Hashimoto et al.
patent: 6128748 (2000-10-01), MacWilliams et al.
patent: 6324118 (2001-11-01), Ooishi
patent: 10-188555 (1998-07-01), None
patent: 11-306758 (1999-11-01), None

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