Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-04-19

2005-04-19

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000

Reexamination Certificate

active

06882557

ABSTRACT:
The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased.The switches are connected to one-side ends of the bit lines provided at the odd-numbered positions, and are connected to the other-side ends of the bit lines provided at the even-numbered positions. A pair of odd-numbered or even-numbered bit lines are connected to the terminals of each sense amplifier, respectively. The memory cells are arranged at predetermined intersection points of the word lies and the bit lines, the number of the predetermined intersection points being equal to half of all the intersection points thereof, in such a manner that when one word line is selected, the memory cells connected to the selected word-line can be electrically connected in such a manner that one memory cell is electrically connected to each terminal of the unit circuits.

REFERENCES:
patent: 6272054 (2001-08-01), Barth, Jr. et al.
patent: 6344990 (2002-02-01), Matsumiya et al.
patent: 6400596 (2002-06-01), Takemura et al.
patent: 2001-143463 (2001-05-01), None

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