Semiconductor memory device

Static information storage and retrieval – Floating gate – Multiple values

Reexamination Certificate

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C365S185210

Reexamination Certificate

active

06947322

ABSTRACT:
A semiconductor memory device is provided, which comprising a memory cell array comprising a two-value memory region and a multi-value memory region, in which the two-value memory region comprises a plurality of memory cells each storing 1-bit data and the multi-value memory region comprises a plurality of memory cells each storing 2 or more-bit data, and a sense amplifier section common to data read of the two-value memory region and data read of the multi-value memory region, for reading data stored in a selected memory cell by comparing a potential of the selected memory cell with a reference potential.

REFERENCES:
patent: 5831900 (1998-11-01), Miyamoto
patent: 6473321 (2002-10-01), Kishimoto et al.
patent: 6771537 (2004-08-01), Jyouno et al.
patent: 2001-202788 (2001-07-01), None

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