Semiconductor memory device

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S185050, C365S189070

Reexamination Certificate

active

06862251

ABSTRACT:
A semiconductor memory device includes a first nonvolatile memory cell, a bit line connected to the first nonvolatile memory cell, and a control circuit connected to the first nonvolatile memory cell and the bit line, and disposed and configured in such a manner as to reset the bit line to a predetermined first potential state only for a certain period “a” of time in response to transition of an input address signal. The first nonvolatile memory cell has a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

REFERENCES:
patent: 5530671 (1996-06-01), Hashimoto
patent: 5555217 (1996-09-01), Hashimoto
patent: 5771196 (1998-06-01), Yang
patent: 6115290 (2000-09-01), Kwong
patent: 5-81072 (1993-11-01), None
patent: 5-304277 (1993-11-01), None
patent: 9-97849 (1997-04-01), None
patent: 9-116119 (1997-05-01), None
patent: 2001-156188 (2001-06-01), None
patent: 2001-230332 (2001-08-01), None
patent: 2001-512290 (2001-08-01), None
patent: WO 99-07000 (1999-02-01), None

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