Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-10-22

2004-08-24

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S185110, C365S185210, C365S185230, C365S189080

Reexamination Certificate

active

06781915

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly relates to improvement in data retention characteristics of a semiconductor memory device storing data in a capacitor. More particularly, the present invention relates to a semiconductor memory device, in which data of one bit is stored by memory cells of two bits. More specifically, the present invention relates to a configuration for ensuring reliability of gate insulating films of memory cells in an embedded memory integrated with a logic on the same semiconductor substrate, without impairing the data retention characteristics.
2. Description of the Background Art
In the field of data processing and others, a circuit device called a system LSI (large scale integrated circuit) having a logic such as a processor and a memory device integrated in a common semiconductor chip has been widely used in order to process data at high speed with low power consumption.
In such system LSI, the configuration in which the logic and the memory device are interconnected through on-chip interconnection lines provides the following advantages: (1) due to smaller load of signal interconnection lines than that of the on-board wires, data/signals can be transmitted at high speed; (2) due to no restriction on the number of pin terminals, the number of data bits can be increased, and the band width of data transfer can be widened; (3) due to integration of a plurality of components on a common semiconductor chip, the size of the system can be reduced compared to the configuration where discrete components are arranged on a board, and thus, a small sized, light-weight system is implemented; and (4) macros prepared as a library can be arranged as the components formed on the semiconductor chip, and thus, design efficiency is improved.
By virtue of the advantages described above, the system LSI has been widely used in various fields. DRAM (dynamic random access memory), SRAM (static random access memory), non-volatile semiconductor memory device and other memory devices have been used for the memory device to be integrated. For the logic to be merged, a processor performing control and processing, an analog processing circuit such as an A/D converter, a logic circuit performing a specialized logical operation and others have been employed.
When integrating a processor and a memory device in the LSI system, it is desired to form the logic and the memory device in the same manufacturing steps as many as possible for the purposes of reducing the number of manufacturing steps and cost. A DRAM stores data in a capacitor in the form of charges. This capacitor has electrodes called a storage node electrode and a cell plate electrode formed above a semiconductor substrate region. Such a memory capacitor is generally called a stacked capacitor, and has a complicated shape like a hollow cylinder to achieve a large capacitance value with a small occupying area.
Thus, in the DRAM-logic hybrid process of forming the DRAM and the logic in the same manufacturing process, even if the transistor of the logic and the transistor of the DRAM are formed in the same manufacturing process, additional manufacturing steps of forming the capacitor of the DRAM, and a planarization process for alleviating unevenness or steps between the DRAM and the logic and between the DRAM memory array and the peripheral portion, due to the three dimensional structure of the capacitor of the DRAM, become necessary. This significantly increases the number of manufacturing steps and also increases the chip cost.
In an SRAM, a memory cell is formed of four transistors and two load elements. Normally, the load elements are formed with MOS transistors (insulated gate type field effect transistors), and capacitors or the like are not used. Accordingly, an SRAM can be formed by a full CMOS logic process, and hence, the SRAM and the logic can be formed in the same manufacturing process.
The SRAM, due to its high speed operability, is conventionally used as a cache memory for a processor, a register file memory or the like.
Further, the SRAM has a memory cell formed of a flip-flop circuit, and data is retained as long as a power supply voltage is supplied. Thus, unlike the DRAM, the SRAM does not require refreshing for retention of data, and complicated memory control associated with the refreshing, indispensable to the DRAM, is unnecessary for the SRAM. Thus, the SRAM, simpler in control than the DRAM, has been widely used as a main memory of a portable information terminal or the like, to simplify the system configuration.
However, a portable information terminal now requires a memory of even larger storage capacity, as it is required to handle a large amount of data such as audio and image data, as its recent progress in functionality.
In the DRAM, the memory cell is shrunk along with the progress of a miniaturization process. For example, a cell size of 0.3 &mgr;m
2
has been implemented according to the 0.18 &mgr;m DRAM process. In contrast, in the SRAM, a full CMOS memory cell consists of six MOS transistors in total with two P channel MOS transistors and four N channel MOS transistors. Therefore, even if the miniaturization process advances, it is necessary to isolate an N well for forming P channel MOS transistors from a P well for forming N channel MOS transistors in a memory cell. The constraints of such an inter-well isolation distance hinder shrinkage of the memory size of the SRAM, compared to the DRAM. For example, in the 0.18 &mgr;m CMOS logic process, the memory size of the SRAM is 7 &mgr;m
2
or so, which is more than 20 times the memory size of the DRAM. Accordingly, if the SRAM is utilized as a main memory of large storage capacity, the chip size will significantly increase. It would be extremely difficult to merge an SRAM of storage capacity of 4 Mbits or more with a logic within a system LSI of limited chip area.
In view of the foregoing consideration, it can be considered to use a DRAM-based memory for the large capacity embedded memory. Such a DRAM-based embedded memory could be manufactured employing conventional manufacturing processes to some extent, using conventional manufacturing apparatus and steps. With this DRAM-based memory, however, there still arises the above-described problem of step of the capacitor as long as data is stored in the capacitor. It would be impossible to form the DRAM-based memory and the logic through the same manufacturing steps.
In addition, portable terminal equipment is battery-powered, and it is required to reduce current consumption to the greatest possible extent from the standpoint of life time of the battery. Refresh in the data holding mode is performed simply for retention of data. If the current consumption required for this refresh could be reduced, a stand-by current will be reduced, and correspondingly, the life time of battery will increase.
A possible way to reduce current consumption in such refresh may be to decrease the number of times of refreshing, or to lengthen refresh intervals. If data retention characteristics of a memory cell can be improved and data holding time can be lengthened, the refresh interval will be lengthened, and accordingly, the current consumption required for the refresh could be reduced.
As a way of improving the data retention characteristics of the DRAM, a word line driving scheme called a boosted word line scheme has been used conventionally, wherein a selected word line is driven to a voltage level higher than a power supply voltage level in order to transmit data of a full VCC level to memory cells. In this boosted word line scheme, bit lines are driven by a sense amplifier to a power supply voltage level and a ground voltage level upon completion of a sensing operation. Thus, a high voltage corresponding to a difference between the voltage on the selected word line and the ground voltage will be applied between the gate and source of the transistor of a selected memory cell. If such a high voltage is applied between

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