Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-09-27

2004-08-03

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S201000, C365S203000

Reexamination Certificate

active

06771558

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device which can perform a test operation at a high frequency without delay of a test time, by generating a burst control signal for maintaining an active state of a column operation as long as a burst length as a short pulse signal in the test operation.
2. Description of the Background Art
FIG. 1
is a block diagram illustrating a conventional semiconductor memory device.
The conventional semiconductor memory device includes a state control unit
1
, a clock buffer
2
, a burst length control unit
3
, a burst end control unit
4
and a precharge control unit
5
. In particular, the state control unit
1
receives external control signals/CS, /RAS, /CAS and /WE, and generates operation commands RACT<0:N>, CACT<0:N> and WTA. The clock buffer
2
receives an external clock signal EXCLK and generates a pulse clock signal CLKP having a short pulse in correspondence with a rising edge of the external clock signal EXCLK and an inverted clock signal CLKB having the opposite phase to the external clock signal EXCLK. Burst length control unit
3
outputs a burst control signal/YBST for maintaining an active state of a column operation as long as a burst length BL according to the column active commands CACT<0:N>. The burst end control unit
4
detects an end point of the burst length BL and outputs a burst end signal YBSTEND notifying burst end by using the burst control signal/YBST. Finally, the precharge control unit
5
generates a precharge signal IPCG for performing a precharge operation of the semiconductor memory device according to the write command WTA with an autoprecharge command.
FIG. 2
is a detailed circuit diagram illustrating the burst end control unit
4
of the semiconductor memory device of FIG.
1
. As shown, the burst end control unit
4
includes a comparing unit
6
that is enabled according to the pulse clock signal CLKP or the inverted clock signal CLKB from the clock buffer
2
selectively transmitted according to a test mode signal TM in order to drive the burst control signal/YBST. The burst end control unit
4
also includes a burst end signal generating unit
7
reset by a power up signal/PWR and configured for generating the burst end signal YBSTEND by using the output signal from the comparing unit
6
.
Within the comparing unit
6
are a PMOS transistor PM
1
and an NMOS transistor NM
1
having their gates commonly connected to receive the inverted signal/YBST of the burst control signal YBST from the control unit
3
and also having their drains commonly connected. A source of the PMOS transistor PM
1
is connected to receive a power voltage VCC. The comparing unit
6
further includes transmission gates TG
1
and TG
2
for selectively transmitting the pulse clock signal CLKP or inverted clock signal CLKB from the clock buffer
2
according to the test mode signal TM and an inverted signal of the test mode signal TM by an inverter INV
1
. An NMOS transistor NM
2
has its gate connected to receive the clock signal CLKP or CLKB selectively transmitted by the transmission gates TG
1
or TG
2
. The drain of NMOS transistor NM
2
is connected to the source of the NMOS transistor NM
1
and its source is connected to a ground voltage VSS.
The burst end signal generating unit
7
includes a latch unit
8
having two inverters INV
2
and INV
3
for latching an output signal COM from the commonly-connected drains of the PMOS transistor PM
1
and the NMOS transistor NM
1
of the comparing unit
6
. Also included is a delay unit
9
having an even number of inverters INV
4
-INV
7
for delaying the output signal from the latch unit
8
for a predetermined time. A NOR gate NOR
1
is configured for NORing the output signal from the delay unit
9
and the output signal COM from the comparing unit
6
. An inverter INV
8
inverts the output signal from the NOR gate NOR
1
and outputs the burst end signal YBSTEND. An NMOS transistor NM
3
resets the output signal COM from the comparing unit
6
to a low level according to the power up signal/PWR.
The operation of the conventional semiconductor memory device will now be explained.
As shown in
FIG. 3
, in a normal mode, the test mode signal TM has a low level, the row active command RACT<0> is inputted to maintain a row active state, and the write command WTA with the autoprecharge command is inputted to perform a write operation. When the burst length BL ends, the burst control signal/YBST is disabled from a low to high level, thereby finishing the write operation. In turn, when the burst control signal/YBST is disabled, the burst end signal YBSTEND is generated as a short pulse in correspondence with the rising edge of the pulse clock signal CLKP.
The burst end signal YBSTEND is next transmitted to the precharge control unit
5
to output the precharge signal IPCG having a short pulse. Accordingly, the semiconductor memory device performs the precharge operation according to the precharge signal IPCG
As depicted in
FIG. 4
, in a test mode, the test mode signal TM has a high level, the row active command RACT<0> is inputted to maintain the row active state, and the write command WTA with the autoprecharge command is inputted to perform the write operation. When the burst length BL ends, the burst control signal/YBST is disabled from a low to high level, thereby finishing the write operation. Next, when the burst control signal/YBST is disabled, the burst end signal YBSTEND is generated as a short pulse in correspondence with the rising edge of the inverted clock signal CLKB.
The burst end signal YBSTEND is next transmitted to the precharge control unit
5
to output the precharge signal IPCG having a short pulse. Therefore, the semiconductor memory device performs the precharge operation according to the precharge signal IPCG.
Since the write operation is performed in correspondence with the falling edge of the inverted clock signal CLKB and the precharge operation is performed in correspondence with the rising edge thereof (i.e., the write operation is performed in correspondence with the rising edge of the external clock signal EXCLK and the autoprecharge operation is performed in correspondence with the falling edge thereof) a clock frequency of a test circuit is increased by two times to perform the test. In addition, the write operation and the precharge operation are carried out in every one clock to reduce a test time.
A parameter indicating a time from an input of data to input of the precharge command (data into precharge command; tDPL) is screened according to the test operation. Here, the burst length BL is set up to be one (1), and the write command WTA with the autoprecharge command is transmitted to the respective unit memory cells in every two clocks. However, the test circuit using the above-described methods requires an operation frequency as high as an operation frequency of the semiconductor memory device, and also requires two clocks to perform the write and precharge operations in every unit memory cell. Hence, in order to precisely screen the parameter tDPL, whenever the operation frequency of the semiconductor memory device is increased, a test circuit must be replaced by a test circuit using the corresponding frequency.
Additionally, since a pulse width of the burst control signal/YBST is determined, when the external clock signal EXCLK having a high frequency is inputted as shown in
FIG. 5
, the burst control signal/YBST is disabled from a low to high level, and the pulse of the burst end signal YBSTEND is generated in correspondence with the rising edge of the inverted clock signal CLKB. The precharge operation is performed by generating the pulse of the burst end signal YBSTEND, not in correspondence with the desired falling edge of the external clock signal EXCLK, but in correspondence with the succeeding falling edge thereof. As a result, the precharge operation is carried out in a time later than

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