Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2000-02-28
2001-10-30
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S907000
Reexamination Certificate
active
06310399
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the field of semiconductors. The present invention relates to a semiconductor memory configuration having word lines and bit lines. Some bit lines are routed over a memory-cell area. Bit lines with a twist run alongside bit lines without a twist, and one bit-line pair with a twist has contacts for one bit line to be crossed over by the other bit line of the pair in a further plane that is different from the bit-line plane.
Conventionally, bit lines are routed over memory-cell areas with a bit-line twist and without a bit-line twist. A bit-line twist has the advantage that the two bit lines that cross each other through the twist are symmetrically coupled capacitively such that possible interference signals cancel each other. In addition, coupling in from adjacent lines is also canceled if “folded” bit lines are involved.
The crossing over of two bit lines in a twist assumes that one of the bit lines is routed over the other bit line at a distance and in an electrically insulated manner. The crossover can be done, for example, by raising one bit line (in relation to the other bit line) in the crossover area into the word-line plane through contacts, such that in the crossover area one bit line runs in the word-line plane, while the other bit line remains on the bit-line plane.
Adjacent bit lines should influence each other as little as possible, that is to say the electrical coupling between such adjacent bit lines should be reduced as far as possible. The reduction can be done by routing the bit lines with a large spacing and without a twist or crossover in relation to one another. However, such a large spacing is necessarily associated with a considerably increased area requirement for the memory-cell area.
In order to avoid the large spacing, the above mentioned twist is introduced. Then, the bit lines can run more closely alongside one another, thus, canceling the interference introduced by the capacitive coupling that is necessarily present as a result of the twist. At present, preference is given to semiconductor memory configurations in which bit lines are provided in pairs, without a twist and with a twist. Such preference means that two bit lines without a twist follow two bit lines with a twist. It has been shown that such a configuration of the bit lines achieves optimization with regard to reducing the effects of the capacitive coupling arising from the twist of each second bit-line pair, simplifies the circuit structure arising from the necessary crossovers for each second pair, and reduces the area required.
However, one disadvantage of configuring a semiconductor memory as set forth above is that in the word-line plane the individual word lines experience different proximity effects at different locations because it is only in the area of the bit-line pairs with a twist that the one bit lines, with their contacts, are routed into the word-line plane. Therefore, different and inhomogeneous affects on the word lines occur in the crossover area of the bit lines in an undesired way.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory configuration with a bit-line twist that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that provides the maximum electrical and geometrical symmetry with a minimum area requirement such that the non-uniform influence of edge elements, specifically word lines, in the crossover or twist area of the bit lines is avoided.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a semiconductor memory configuration, including bit lines in a bit-line plane, a further plane different from the bit-line plane, word lines, and a memory cell area adjacent the bit-line plane, some of the bit lines having a twist running alongside others of the bit lines being untwisted, pairs of the some of the bit lines with a twist each respectively defining a twist bit-line pair, the twist bit-line pair having contacts for crossing one bit line of the twist bit-line pair over another bit line of the twist bit-line pair and over the memory-cell area through the further plane, the untwisted others of the bit lines having dummy contacts leading from the bit-line plane to the further plane.
In accordance with another feature of the invention, the further plane is a word-line plane and the word lines are in the word-line plane.
In accordance with a further feature of the invention, the bit-line plane has a twist area including the twist of the some of the bit lines and a twist-free area, and the bit lines in the twist-free area are approximately from 150 nm to 250 nm wide.
In accordance with an added feature of the invention, the twist area only includes the twist of the some of the bit lines.
In accordance with an additional feature of the invention, the bit lines in the twist-free area are approximately 200 nm wide.
In accordance with yet another feature of the invention, the bit-line plane has a twist area including the twist of the some of the bit lines and the some of the bit lines in the twist area are approximately from 250 nm to 350 nm wide.
In accordance with yet a further feature of the invention, some of the bit lines in the twist area are approximately 330 nm wide.
In accordance with yet an added feature of the invention, the bit lines have spacing between each other approximately from 150 to 180 nm wide.
In accordance with a concomitant feature of the invention, the bit lines, the word lines, the contacts, and the dummy contacts are selected from the group consisting of copper and aluminum.
As a result of the dummy contacts, edge elements in the further plane that, in the twist area, adjoin the contacts of the bit lines, have the same electrical “environment,” so that different proximity effects are avoided. Therefore, the bit lines can be routed with high area efficiency, extremely homogeneously and, both electrically and geometrically, in a largely symmetrical manner, so that no problems are caused with edge elements in the crossover area.
The memory-cell area located under the bit lines is completely regular in the area of the crossover or of the twist, so that no additional edge areas result in the memory-cell area either, and the introduction of special edge elements is not necessary. As a result of the close routing of the bit lines alongside one another, the area requirement is also desirably and advantageously kept low.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory configuration with a bit-line twist, it is nevertheless not intended to be limited to the details shown, because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5747844 (1998-05-01), Aoki et al.
patent: 5821592 (1998-10-01), Hoenigschmid et al.
patent: 5864181 (1999-01-01), Keeth
patent: 6066870 (2000-05-01), Siek
Feurle Robert
Mandel Sabine
Savignac Dominique
Schneider Helmut
Chaudhuri Olik
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Pham Hoai
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