Semiconductor memory comprising an on-chip error correction devi

Details Semiconductor memory comprising an on-chip error correction devi Semiconductor memory comprising an on-chip error correction devi

1990-05-22

1991-06-04

Jablon, Clark A.

Excavating

371 404, G06F 1110

Patent

active

050220314

ABSTRACT:
A description is given of a semiconductor memory with an on-chip error correction facility. The code used is defined over the location domain of the columns. The columns are arranged in patterns of non-redundant and redundant memory cells which recur with a fixed period. As a result of the convolution code chosen, decoding is possible by way of a small number of series connected gates, so that the time delay is limited. The correction capability of the code is only partly used because complete use could cause additional delay.

REFERENCES:
patent: 4604749 (1986-08-01), Shinoda

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