Semiconductor memory column decoder device and method

Details Semiconductor memory column decoder device and method Semiconductor memory column decoder device and method

2011-08-16

2011-08-16

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270, C365S185170, C365S185290

Reexamination Certificate

active

08000151

ABSTRACT:
Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.

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