Semiconductor memory circuit with improved timing and delay cont

Details Semiconductor memory circuit with improved timing and delay cont Semiconductor memory circuit with improved timing and delay cont

1987-04-08

1989-06-20

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 36518901, 36518907, G11C 700, G11C 1140

Patent

active

048414883

ABSTRACT:
A memory circuit which can be reset to an inactive stand-by mode rapidly as soon as a chip select signal is changed to an inactive level, is disclosed. The memory circuit employs a first internal control signal for enabling a selection circuit for memory cells and a second internal control signal for enabling an output circuit and is featured in that the first control signal is activated more rapidly then the second control signal in response to the active level of the chip select signal and the second control signal is deactivated more rapidly than the first control signal in response to the inactive level of the chip select signal.

REFERENCES:
patent: 4337523 (1982-06-01), Hotta et al.
patent: 4573145 (1986-02-01), Ozawa
patent: 4679173 (1987-07-01), Sato
patent: 4682048 (1987-07-01), Ishimoto
patent: 4710903 (1987-12-01), Hereth et al.

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