Semiconductor memory circuit with depletion data transfer transi

Details Semiconductor memory circuit with depletion data transfer transi Semiconductor memory circuit with depletion data transfer transi

1981-08-21

1983-06-21

Hecker, Stuart N.

Static information storage and retrieval

Read only systems

Semiconductive

365203, G11C 1700, G11C 700

Patent

active

043897053

ABSTRACT:
A read only memory (ROM) circuit (10) includes a memory storage transistor (16) which is fabricated to have one of a plurality of threshold voltages corresponding to predetermined data states. The source and drain terminals of the memory transistor (16) are connected between a column node (18) and a bit line (20). A lightly depleted data transfer transistor (30) is connected between the bit line (20) and a data line (14). The column node (18), bit line (20) and data line (14) are precharged. A memory address is decoded to drive a selected word line (12) and a selected column decode line (32) to a high voltage state. A transistor (34) discharges the column node (18). Depending upon the state of the memory storage transistor (16) the bit line (20) is discharged or maintained precharged. The state of bit line (20) is transmitted through the data transfer transistor (30) to the data line (14). The data transfer transistor ( 30) can be fabricated as a relatively small device due to the large turn on voltage applied thereto because the transistor (30) is a depletion device. The smaller size of a plurality of the transistors (30) results in a substantial saving in space and reduces capacitive loading on the data line (14) thereby speeding up the discharge rate of the data line (14).

REFERENCES:
patent: 3728696 (1973-04-01), Polkinghorn
patent: 3848236 (1974-11-01), Troutman

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