Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-07-17
2001-07-10
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S236000
Reexamination Certificate
active
06259649
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory circuit and, in particular, to a semiconductor memory circuit layout capable of reducing the number of wires on the layout of a semiconductor memory.
2. Description of the Prior Art
FIG. 1
illustrates a semiconductor memory with a conventional Lead-On-Chip(LOC) architecture which is equipped with a peripheral circuit block
10
for applying data, control signals or address signals between a plurality of memory cell arrays for storing data.
As shown therein, the peripheral circuit block
10
includes an input/output pad
15
for inputting and outputting data to be stored in memory cells, an address and control pad
14
for inputting an address signal and a control signal, an address counter
12
for counting the address signal, address counter buffers
13
-L and
13
-R for buffering the address signal applied from the address counter
12
, and address decoders
11
-L and
1
for decoding the inputted address signal.
A general synchronous semiconductor memory requires the address counter
12
for counting from a certain particular address. In order to transmit the output of the address counter
12
to the address decoders
11
-L and
11
-R, buffering is performed using the buffers
13
-L and
13
-R.
Generally, when a pad type memory with a LOC architecture is used, the address counter
12
is placed at the center of the address pad
14
. This is for maintaining the setup and hold margin between an address input pad and a clock pad.
Therefore, the address counter
12
is not placed at the center of a chip, but placed at the center of the address pad
14
. The output of the address counter
12
is buffered by the two address counter buffers
13
-L and
13
-R at the center of a chip and then transmitted to the address decoders
11
-L and
11
-R at the left and right sides of the chip, respectively.
Herein, the reason why the address counter buffers
13
-L and
13
-R are placed at the center of the chip is to transmit a counter output of the same load to the address decoders
11
-L and
11
-R at both sides.
Especially, as the capacity of the semiconductor memory becomes larger, the distance between the address counter
12
and the address decoders
11
-L and
11
-R is lengthened, so that the necessity for the address counter buffers
13
-L and
13
-R increases.
In the layout of the above-described semiconductor memory chip, the layout area of an unit circuit block has been a primary factor in determining the size of the entire chip in the conventional art. However, as the semiconductor memory is highly-integrated, the routing between unit circuit blocks becomes a primary factor in determining the size of the chip rather than the layout area of an unit circuit block.
However, in the case of using a conventional technique as illustrated in
FIG. 1
, there is a problem that since 2A
N
(A
N
number of addresses) number of wires is required at the left portion of the chip at which the output of the address counter
12
and the output of the left address counter buffer
13
-L overlap and accordingly the number of wires is increased by A
N
compared to the right portion of the chip, the size of the chip is increased as much.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory circuit capable of reducing the number of wires by differentiating the layout of address counter buffers.
To achieve the above objects, there is provided a synchronous semiconductor memory circuit with a LOC architecture including a peripheral circuit block in which an address pad and an input/output pad are arranged at the left and right sides of a chip, respectively, wherein an address counter is placed at the center of the address pad, a first address decoder is placed at the address pad, a second address decoder is placed at the input/output pad, a first address counter buffer for driving the first address decoder upon receipt of the output of the address counter is placed adjacent to the address counter between the address counter and the first address decoder, and a second address counter buffer for driving the second address decoder upon receipt of the output of the address counter is placed at the center of the chip.
REFERENCES:
patent: 4618947 (1986-10-01), Tran et al.
patent: 5721859 (1998-02-01), Manning
patent: 6052331 (2000-04-01), Araki et al.
patent: 6088252 (2000-07-01), Fujisawa et al.
Hyundai Electronics Industries Co,. Ltd.
Phan Trong
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