Semiconductor memory circuit

Details Semiconductor memory circuit Semiconductor memory circuit

1993-03-12

1994-03-22

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, G11C 800

Patent

active

052971058

ABSTRACT:
A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First to third memory cell blocks respectively have memory cell groups each including memory cells. First to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal. Third and fourth logic circuits respectively, in response to the second and the first information, apply first common decode signals to the first and second decoder groups upon the first common block selection signal being outputted, and a plurality of second common decode signals to the second and third decoder groups upon the second common block selection signal being outputted. In response to the first and second common decode signals, a second decoder in the second decoder group is activated so as to select one memory cell group in the second memory cell block.

REFERENCES:
patent: 4660178 (1987-04-01), Hardee et al.
patent: 4811297 (1989-03-01), Ogawa
patent: 4849943 (1989-07-01), Ptennings
patent: 5161121 (1992-11-01), Cho
patent: 5237536 (1993-08-01), Ohtsuki

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