Semiconductor memory circuit

Details Semiconductor memory circuit Semiconductor memory circuit

1991-05-20

1994-01-11

Sikes, William L.

Static information storage and retrieval

Addressing

36518901, 365222, 36523006, G11C 700

Patent

active

052787990

ABSTRACT:
A semiconductor memory circuit in which data are stored in dynamic type memory cells located at cross-points of bit and word lines, and are refreshed within a predetermined time by a sense amplifier so as to hold the thus stored data includes a first bit line connected to a first sense node of the sense amplifier. A second bit line is connected to a second sense node of the sense amplifier. A first switching circuit having a first terminal is disposed between the first bit line and the first sense node, for coupling the first bit line with the first sense node in response to a first control signal applied to the first terminal. A second switching circuit having a second terminal is disposed between the second bit line and the second sense node, for coupling the second bit line with the second sense node in response to a second control signal applied to the second terminal. A first control line is coupled to the first terminal and isolated from the second switching circuit and the second bit line, for providing the first control signal. A second control line is coupled to the second terminal and isolated from the first switching circuit and the first bit line, for providing the second control signal.

REFERENCES:
patent: 4367538 (1983-01-01), Shimada
patent: 4500974 (1985-02-01), Nagami
patent: 4710902 (1987-12-01), Pelley, III et al.
patent: 4800525 (1989-01-01), Shah et al.
patent: 4982370 (1991-01-01), Matsumoto et al.
patent: 5075887 (1991-12-01), Magome et al.

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