Semiconductor memory chip

Details Semiconductor memory chip Semiconductor memory chip

2007-05-22

2007-05-22

Phan, Trong (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189050, C365S230080, C365S233100, C714S763000

Reexamination Certificate

active

11242150

ABSTRACT:
A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

REFERENCES:
patent: 5369617 (1994-11-01), Munson
patent: 5737563 (1998-04-01), Shigeeda
patent: 5898623 (1999-04-01), Clinton et al.
patent: 5950223 (1999-09-01), Chiang et al.
patent: 6000007 (1999-12-01), Leung et al.
patent: 6028807 (2000-02-01), Awsienko
patent: 6178517 (2001-01-01), Bertin et al.

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