Semiconductor memory cells and semiconductor memory device emplo

Details Semiconductor memory cells and semiconductor memory device emplo Semiconductor memory cells and semiconductor memory device emplo

1989-08-21

1990-11-13

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read only systems

Fusible

3652257, 357 51, G11C 1716

Patent

active

049706861

ABSTRACT:
A spare memory cell comprises a read FET (Field Effect Transistor), a fusing FET and a current fuse. The FETs are connected in series between a read data line and a low voltage source. The fuse is inserted between a series node of the FETs and a write data line. The fuse is molten when data is written to the spare memory cell. By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line, the fusing FET is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET to cut off the fuse, thus writing data to the spare memory cell.

REFERENCES:
patent: 4223277 (1980-09-01), Taylor et al.
patent: 4399372 (1983-09-01), Tanimoto et al.
patent: 4494220 (1985-01-01), Dumbri et al.
patent: 4546455 (1985-10-01), Iwahashi et al.
patent: 4609998 (1986-09-01), Basnyak et al.
patent: 4698589 (1987-10-01), Blankenship et al.

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