Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2000-02-16
2001-01-09
Phan, Throng (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
Reexamination Certificate
active
06172894
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor memory cells and more particularly to a semiconductor memory cell having only two signal input terminals for more than two combinations of binary signals to be stored in the cell and including circuitry for storing more than two stable states.
BACKGROUND ART
Typical prior art semiconductor memory cells have only two stable states for storing complementary bit levels. In a first of the states the cell stores a binary zero level, and in a second of the states the cell stores a binary one level. The cell typically includes first and second output terminals such that when the cell stores a binary zero level the cell respectively supplies low and high voltages to the first and second tenninals; when the cell stores a binary one level the cell respectively supplies high and low voltages to the first and second output terminals. The typical cell also includes first and second signal input tenninals responsive to complementary bi-level voltages such that when a binary zero level is written into the cell, low and high voltages are respectively applied to the first and second input terminals; when a binary one level is written into the cell the first and second input terminals are respectively responsive to high and low voltage levels.
The typical prior art semiconductor memory cell includes first and second inverters connected to each other in a back-to-back regenerative feedback arrangement. Each of the inverters has an input and output terminal such that the output terminal of the first inverter is connected to the input terminal of the second inverter and the output terminal of the second inverter is connected to the input terminal of the first inverter. In essence, the output terminals of the first and second inverters are the first and second output terminals of the cell from which the binary state of the cell is read during a read operation. The voltage levels at the first and second input terminals are respectively supplied to input terminals of first and second write lines or leads via gates that are open during a write operation. In the typical integrated circuit semiconductor memory, the gates are referred to as pass gates, each formed by a source drain path of a field effect transistor (FET) having a gate electrode responsive to a write pulse source. The voltage levels at the cell first and second output terminals are supplied to first and second data lines or leads that are coupled to a read logic network on an integrated chip including the memory cells.
A substantial amount of the area of each cell is occupied by the write and data lines. The write and data lines occupy a considerably greater area of each cell than the active elements, i.e., field effect transistors (FETs), forming the inverters of each cell. To maximize packing density of each cell on the integrated circuit chip, it is desirable to maximize the use of the write and data lines of each memory cell.
SUMMARY OF THE INVENTION
I have realized that greater packing density can be achieved by modifying the circuitry of the typical prior art cell so that it can store more than two states, without modifying the write and data lines associated with each cell. Consequently, the area of a cell is not increased appreciably because the cell basic geometry including the write and data lines has not been altered. This is true even though the cell circuitry is modified to include an increased number of active devices. Because the write and data lines occupy a considerably higher percentage of the cell area than the active devices, the change in the cell active device complement does not substantially increase cell area.
The result is achieved by supplying more than two combinations of binary voltage levels to the cell first and second input terminals and by arranging the cell so that it can supply more than two combinations of binary voltage levels to the cell data lines. In the preferred embodiment, the cell input terminals are responsive to three combinations of binary input signals, namely (0,1), (1,0) and (0,0). However, the concept of the invention is not limited to these three combinations and is expandable to include all four combinations of the binary levels that can be applied to the first and second input terminals of the cell, i.e., (0,0), (0,1), (1,0) and (1,1).
It is, accordingly, an object of the present invention to provide a new and improved semiconductor memory having cells for storing more than two binary levels.
Another object of the present invention is to provide a new and improved semiconductor memory cell having an area that is not substantially greater than typical prior art cells, but which is capable of storing more than two binary levels.
An additional object of the invention is to provide a new and improved semiconductor memory having cells for storing more than two binary levels, wherein each cell includes the same complement of write and data lines as prior art cells having a similar cell geometry.
According to one aspect of the invention, a semiconductor memory cell for storing more than two binary states comprises first and second signal input terminals that are responsive to more than two combinations of binary levels of first and second binary sources. Active circuit elements having inputs connected to be responsive to voltages at the first and second input terminals supply voltages to first and second data lines of the cell so that the cell stores and supplies to the first and second data lines (a) a first combination of binary voltage levels in response to the first and second binary sources writing a first combination of binary levels into the cell via the first and second signal input terminals, (b) a second combination of binary voltage levels in response to the first and second binary sources writing a second combination of binary levels into the cell via the first and second signal input terminals and (c) a third combination of binary voltage levels in response to the first and second binary sources writing a third combination of binary levels into the cell via the first and second signal input terminals.
Another aspect of the invention relates to a semiconductor memory cell that responds to first and second binary sources and stores three combinations of values of the first and second binary sources. The cell includes first and second latches, each having first and second storage nodes. The first and second storage nodes of the first latch are respectively responsive to the first and second binary sources during a write operation of the cell. The first and second nodes of the second latch are respectively responsive to the second and first binary sources during the write operation. Each of the latches includes substantially identical circuitry including (a) first and second inverters selectively connected in a regenerative back-to-back relation between the first and second nodes, and (b) a control circuit responsive to the bit at one of the nodes for controlling the connections of the inverters to each other.
An additional aspect of the invention concerns a semiconductor memory cell that responds to first and second binary sources and stores three combinations of values of the first and second binary sources. The cell comprises first and second latches, each having first and second storage nodes. The first and second nodes of the first latch are respectively responsive to the first and second binary sources during a write operation of the cell. The first and second nodes of the second latch are respectively responsive to the second and first binary sources during the write operation. Each of the latches includes substantially identical circuitry including first and second inverters selectively connected in a regenerative back-to-back relation between the first and second nodes. A control circuit enables the inverters to store more than two combinations of the values of the bits of the binary sources.
Hence the cell preferably includes first, second, third and fourth inverters, each including an input te
Hewlett--Packard Company
Phan Throng
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