Semiconductor memory cell capacitor and fabrication method there

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437 47, 437 60, 437919, H01L 2170

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054808243

ABSTRACT:
A capacitor of a semiconductor memory cell having a maximized capacitance and a process for formation thereof are disclosed. The process is characterized in that a projected portion or a depressed portion is formed. Sets of polysilicon layers and silicon oxide layers are stacked over the projected or depressed portion. The sets of stacked layers are etched back, so that the layers having a slower etch rate remain in the form of multi-layer rims. An underlying silicon oxide layer is etched using the multi-layer rims as a mask to form a multi-layer cylinder. Then a polysilicon layer is deposited and etched back deeper than the thickness of the polysilicon layer. The silicon oxide layer is subjected to a wet etch to form a multi-layer cylindrical storage electrode. Then a dielectric layer and cell plate are formed on the storage electrode.

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