Semiconductor memory cell and method of manufacturing the same

Details Semiconductor memory cell and method of manufacturing the same Semiconductor memory cell and method of manufacturing the same

2000-03-29

2002-02-12

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185010, C257S365000, C257S369000, C257S311000, C257S314000, C257S300000, C257S272000, C257S263000, C257S288000, C257S262000

Reexamination Certificate

active

06347050

ABSTRACT:

BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a semiconductor memory cell comprising at least 3 transistors, a transistor for read-out, a transistor for write-in and a junction-field-effect transistor for current control, a semiconductor memory cell comprising a transistor for read-out, a transistor for write-in, a junction-field-effect transistor for current control and at least 1 diode, a semiconductor memory cell comprising at least 4 transistors, a transistor for read-out, a transistor for write-in, a junction-field-effect transistor for current control and a third transistor for write-in, or a semiconductor memory cell comprising a transistor for read-out, a transistor for write-in, a junction-field-effect transistor for current control, a third transistor for write-in and at least 1 diode, and a method of manufacturing the above semiconductor memory cell.
As a high-density semiconductor memory cell, there has been made available a dynamic semiconductor memory cell that can be said to be a single-transistor semiconductor memory cell including one transistor and one capacitor shown in FIG.
56
. In the above semiconductor memory cell, an electric charge stored in the capacitor is required to be large enough to generate a sufficiently large voltage change on a bit line. However, as the planar dimensions of the semiconductor memory cell are reduced, the capacitor formed in a parallel planar shape decreases in size, which causes a new problem that, when information which is stored as an electric charge in the capacitor of the memory cell is read out, the read-out information is buried in noise, or that only a small voltage change is generated on the bit line since the stray capacitance of the bit line increases each time a new generation of the semiconductor memory cell is introduced. As means for solving the above problems, there has been proposed a dynamic semiconductor memory cell having a trench capacitor cell structure shown in
FIG. 57
or a stacked capacitor cell structure. Since, however, the fabrication-related technology has its own limits on the depth of the trench (or the groove) or the height of the stack, the capacitance of the capacitor is also limited. For this reason, dynamic semiconductor memory cells having the above structures are said to reach the limit of dimensions smaller than those of the low sub-micron rules unless expensive new materials are introduced for the capacitor.
In the planar dimensions smaller than those of the low sub-micron rule, the transistor constituting the semiconductor memory cell also has problems of deterioration of the dielectric strength characteristic and punchthrough. There is therefore a large risk that current leakage arises even if the voltage applied to the semiconductor memory cell is still within a predetermined range. When a semiconductor memory cell is made infinitesimal in size, therefore, it is difficult to normally operate the semiconductor memory cell having a conventional transistor structure.
For overcoming the above limit problems of the capacitor, the present applicant has proposed a semiconductor memory cell comprising two transistors or two transistors physically merged into one unit, as is disclosed in Japanese Patent Application No. 246264/1993 (Japanese Patent Laid-open No. 99251/1995), corresponding to U.S. Pat. No. 5,428,238. The semiconductor memory cell shown in FIGS.
15
(A) and
15
(B) of Japanese Patent Laid-Open No. 99251/1995 comprises a first semi-conductive region SC
1
of a first conductivity type formed in a surface region of a semiconductor substrate or formed on an insulating substrate, a first conductive region SC
2
formed in a surface region of the first semi-conductive region SC
1
so as to form a rectifier junction together with the first semi-conductive region SC
1
, a second semi-conductive region SC
3
of a second conductivity type formed in a surface region of the first semi-conductive region SC
1
and spaced from the first conductive region SC
2
, a second conductive region SC
4
formed in a surface region of the second semi-conductive region SC
3
so as to form a rectifier junction together with the second semi-conductive region SC
3
, and a conductive gate G formed on a barrier layer so as to bridge the first semi-conductive region SC, and the second conductive region SC
4
and so as to bridge the first conductive region SC
2
and the second semi-conductive region SC
3
, the conductive gate G being connected to a first memory-cell-selecting line, the first conductive region SC
2
being connected to an information write-in setting line, and the second conductive region SC
4
being connected to a second memory-cell-selecting line.
The first semi-conductive region SC
1
(to function as a channel forming region Ch
2
), the first conductive region SC
2
(to function as one source/drain region), the second semi-conductive region SC
3
(to function as the other source/drain region) and the conductive gate G constitute a switching transistor TR
2
. On the other hand, the second semi-conductive region SC
3
(to function as a channel forming region Ch
1
), the first semi-conductive region SC
1
(to function as one source/drain region), the second conductive region SC
4
(to function as the other source/drain region) and the conductive gate G constitute an information storing transistor TR
1
.
When information is written in the above semiconductor memory cell, the switching transistor TR
2
is brought into an on-state. As a result, the information is stored in the channel forming region Ch
1
of the information storing transistor TR
1
as a potential or as an electric charge. When the information is read out, a threshold voltage of the information storing transistor TR
1
seen from the conductive gate G varies, depending upon the potential or the electric charge stored in the channel forming region Ch
1
of the information storing transistor TR
1
. Therefore, when the information is read out, the storage state of the information storing transistor TR
1
can be judged from the magnitude of a channel current (including a zero magnitude) by applying a properly selected potential to the conductive gate G. The information is read out by detecting the operation state of the information storing transistor TR
1
.
That is, when the information is read out, the information storing transistor TR
1
is brought into an on-state or an off-state, depending upon the information stored therein. Since the second conductive region SC
4
is connected to the second memory-cell-selecting line, a large current or a small current may flow in the information storing transistor TR
1
, depending upon the stored information (“0” or “1”). In this way, the information stored in the semiconductor memory cell can be read out by utilizing the information storing transistor TR
1
.
However, when the information is read out, the semiconductor memory cell has no mechanism for controlling the current which flows through the first semi-conductive region SC
1
sandwiched by the first conductive region SC
2
and the second semi-conductive region SC
3
. Therefore, when the information stored in the information storing transistor TR
1
is detected with the conductive gate G, only a small margin of the current which flows between the first semi-conductive region SC
1
and the second conductive region SC
4
is obtained, which causes a problem that the number of the semiconductor memory cells connected to the second memory-cell-selecting line (a bit line) is limited.
OBJECT AND SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor memory cell which attains the stable performance of transistors, a large window (current difference) for reading out information stored therein and permits infinitesimal dimensions or to provide a logic semiconductor memory cell.
Further, it is an object of the present invention to provide a semiconductor memory cell comprising at least 3 transistors, a transistor for read-out, a transistor for write-in and a junction-

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