Semiconductor memory cell and memory array with inversion layer

Details Semiconductor memory cell and memory array with inversion layer Semiconductor memory cell and memory array with inversion layer

1991-09-12

1994-03-01

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

257315, 257321, G11C 1140

Patent

active

052914399

ABSTRACT:
A memory cell, suitable for electrically erasable programmable read only memories (EEPROMs), includes direct write cell capability. The memory cell is fabricated on a substrate and uses an inversion source gate disposed above the substrate to generate a depletion source therein. The depletion source defines a channel region in the substrate with an associated drain. An electrically isolated floating gate is disposed above the substrate so as to overlap at least a portion of the substrate channel region. Further, a program gate is disposed to overlap a portion of the floating gate and an access gate is also provided aligned at least partially over the substrate channel region such that a dual gate device is defined. An array of such memory cells can also be constructed.

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