Semiconductor memory cell

Details Semiconductor memory cell Semiconductor memory cell

1992-05-19

1994-08-02

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257369, 257 69, H01L 2701

Patent

active

053348613

ABSTRACT:
A semiconductor memory cell (10) including cross coupled CMOS transistors (12, 14) wherein an N-channel transistor (20) overlies a central portion of each of a first and second active regions (13, 13') at a position intermediate to two word lines (40, 42) which overlie end portions of the active regions (13, 13'). P-channel pull-up transistors (18, 22) overlie the N-channel transistors (16, 20) and share common intermediate gate electrodes (27, 29). Staggered bit line contacts (48, 50) are formed to each active region (13, 13') adjacent to each word line (40, 42) and opposite to the N-type transistors (16, 20). Staggered Vss contacts (52, 54) are provided to each active region (13, 13') adjacent to the word lines (40, 42) and opposite to the bit line contacts (48, 50). A Vss signal is electrically coupled to the N-channel transistors (16, 20) by a doped region (21) formed in the first and second active regions (13, 13' ) which cross under the word lines (40, 42). A Vss contact land (71) is provided by a conductive body overlying the active region in the staggered Vss contacts (52, 54) and a portion of the adjacent word lines (40, 42) and at least a portion of the CMOS transistors (12, 14) opposite the word lines (40, 42).

REFERENCES:
patent: 4543592 (1985-10-01), Itsumi et al.
patent: 4581623 (1986-04-01), Wang
patent: 4918510 (1990-04-01), Pfiester
patent: 5001539 (1991-03-01), Inoue et al.
patent: 5072275 (1991-02-01), Vora
patent: 5132771 (1992-07-01), Yamanaka
patent: 5241193 (1993-08-01), Pfiester et al.
K. Itabashi, et al., "A Split Wordline Cell for 16Mb SRAM Using Polysilicon Sidewall Contacts", IEEE Int. Electron Device Meet., Washington, D.C., Dec. 1992, pp. 477-480.
H. Ohkubo, et al., "16Mbit SRAM Cell Technologies for 2.0V Operations", IEEE Int. Electron Device Meet., Washington D.C., Dec. 1991, pp. 480-484.

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