Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1996-04-15
1997-10-21
Nelms, David C.
Static information storage and retrieval
Addressing
Plural blocks or banks
365 49, 36523005, G11C 700
Patent
active
056803630
ABSTRACT:
In an operation of transferring data between a DRAM array and an SRAM array through a bidirectional transfer gate circuit, data blocks on a selected one in the DRAM array are sequentially selected in a high speed mode, word lines are sequentially selected in the SRAM array, so that data is transferred in a time division multiplexing manner between the DRAM array and the SRAM array in units of data block. A cache block size in a semiconductor memory device containing a cache can be externally changed depending on the application with the internal configuration maintained unchangedly.
REFERENCES:
patent: 5014195 (1991-05-01), Farrell
patent: 5226009 (1993-07-01), Arimoto
patent: 5226147 (1993-07-01), Fujishima
patent: 5343437 (1994-08-01), Johnson
patent: 5353427 (1994-10-01), Fujishima
Dosaka Katsumi
Kumanoya Masaki
Mai Son
Mitsubishi Denki & Kabushiki Kaisha
Nelms David C.
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