Semiconductor memory capable of successively accessing cell arra

Details Semiconductor memory capable of successively accessing cell arra Semiconductor memory capable of successively accessing cell arra

1999-05-06

1999-10-26

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 365202, G11C 800

Patent

active

059739916

ABSTRACT:
In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted and a third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, a high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for a semiconductor chip size.

REFERENCES:
patent: 5438548 (1995-08-01), Houston
Yasuharu Sato et al.; Symposium on VLSI Circuits Digest of Technical Papers; "Fast Cycle RAM (FCRAM); a 20-ns Random Row Access, Pipe-Lined Operating DRAM"; Jun. 1998.

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