Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-01-17
2001-11-13
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185210, C365S185220
Reexamination Certificate
active
06317361
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Japanese Patent Application No. 2000-014004, filed Jan. 19, 2000, the entire disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory for storing analog signals in memory cells. Specifically, the semiconductor memory can detect defective data in the memory cells, and then compensate the defective data, and finally output the analog signal with very little noise.
2. Description of the Related Art
Non-volatile memory, such as EEPROM and flash EPROM storing analog signals, is disclosed in U.S. Pat. No. 5,638,320. Such a non-volatile memory stores the analog signals that correspond to respective one of data writing threshold voltages Vrt of memory cell transistors. The analog signal stored in one memory cell is read out (or restored) by measuring a threshold voltage of the memory cell transistor. The relationship between the threshold voltage of the memory cell transistor and the analog signal is shown in FIG.
11
. The threshold voltages Vt of memory cell transistors storing analog signals are n a range between a minimum read-out voltage Vrtmin and a maximum read-out voltage Vrtmax, which is higher than an initial threshold voltage Vtint. The initial threshold voltage Vtint means a threshold voltage of a memory cell during the erase. The analog signal is stored by controlling precisely the amount of charge to be injected onto the floating gate of the memory cell transistor. Channel-hot-electron-injection is generally used to write an analog signal in the memory cell.
FIG. 12
shows a relationship between a saturation threshold voltage Vrt of the memory cell transistor and a total accumulated write time, when control gate voltage Vpp is changed in the range of 8v~13v during the data writing operation of the flash EPROM. By changing the control gate voltage Vpp, the amount of charge in the floating gate is changed. As a result, a saturation threshold voltage Vst of the memory cell is changed. When the Channel-hot-electron-injection is used, the higher the control gate voltage Vpp, the higher the saturation threshold voltage Vst.
On some occasions, even if these non-volatile memories are used in an electronic product, the charge stored in the memory cell may leaks accidentally. This phenomenon is called a “data holding characteristic defect” (hereinafter referred to as “defective data”). When a memory cell containing defective data is selected to be read out, an analog signal having a minimum voltage, which is not the analog signal to be read out, is read out. For example, when the memory cell at the address N has defective data, and analog signals having high voltages are stored in the memory cells at the addresses N−1 and N+1, which precede or follow the address N, a large distortion is included on the waveform of the analog signal outputted.
SUMMARY OF THE INVENTION
An objective of the invention is to provide a semiconductor memory in which detection of defective data in the memory cells is possible, and in which it is possible then to compensate the defective data and finally output the analog signal without distortion on its waveform.
These objectives are achieved by providing a semiconductor memory including a plurality of memory cells storing data, each cell having a different threshold voltage that is set in a range between a minimum read-out voltage and a maximum read-out voltage, a gate voltage generating circuit applying a first voltage, which is less than the minimum read-out voltage to the gate of the memory cells when a data read-out operation is started, and a sense amplifier applying a first signal to the gate voltage generating circuit when data in the memory cell is read out by the first voltage, and applying a second signal to the gate voltage generating circuit when data in the memory cell is not read out by the first voltage, whereby it is determined that the defective data is stored in the memory cell when the first signal is outputted from the sense amplifier.
Further, these objectives are achieved by providing a semiconductor memory decried above further including the characteristic that the gate voltage generating circuit increases the first voltage when the gate voltage generating circuit receives the second signal.
Moreover, these objectives are achieved by providing a semiconductor memory decried above further including the characteristic that the output from the sense amplifier is changed from the first signal to the second signal when the memory cell is read-out by the increased first voltage, and wherein the gate voltage generating circuit halts the increase the first voltage by receiving the first signal and outputs a voltage as a threshold voltage of the memory cell at the time that the increase is halted.
Furthermore, these objectives are achieved by providing a semiconductor memory decried above further including the characteristic that the plurality of memory cells includes a first memory cell having a first analog signal, which is accessed to read out in a first cycle and a second memory cell having a second analog signal, which is accessed to read out in a second cycle, and a voltage holding circuit holding a increased voltage as a first threshold voltage when the first memory cell is read-out by the increased first voltage in the first cycle, and refusing to hold the first voltage when the second memory cell is read-out by the first voltage in the second cycle and maintaining the first threshold voltage of the first cycle in the second cycle and an analog signal output circuit outputting analog signals, which correspond to the voltages held in the voltage holding circuit.
REFERENCES:
patent: 5638320 (1997-06-01), Wong et al.
patent: 5748526 (1998-05-01), Lee
patent: 5835426 (1998-11-01), Koura
patent: 5966330 (1999-10-01), Tang et al.
patent: 6188603 (2001-02-01), Takeda
patent: 6236591 (2001-05-01), Pockrandt
Watanabe Ken'ichi
Yoshida Takuji
Mai Son
Mimura Junichi
OKI Electric Industry Co., Ltd.
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