Semiconductor memory array with buried drain lines and methods t

Details Semiconductor memory array with buried drain lines and methods t Semiconductor memory array with buried drain lines and methods t

1997-11-24

1999-11-16

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 36518502, 36518501, G11C 1604

Patent

active

059869348

ABSTRACT:
A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

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patent: 5280446 (1994-01-01), Ma et al.
patent: 5544103 (1996-08-01), Lambertson
patent: 5572054 (1996-11-01), Wang et al.
patent: 5717636 (1998-02-01), Dallabora et al.
patent: 5745417 (1998-04-01), Kobayashi et al.
Sohrab Kianian et al., "A Novel 3 Volts-Only, Small Sector Erase, High Density Flash E.sup.2 PROM" 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 71-72.
Y. Ma et al., "A Novel High Density Contactless Flash Memory Array Using Split-Gate Source-Side-Injection Cell For 5V-Only Applications" 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 49-50.

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